This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device of the dual port configuration having serially accessable output ports and random-accessable output ports.
In recent years, in various fields, there has been increased high speed requirement for semiconductor devices, and there has been increased demand for serially accessable devices. For such serially accessable memory device, there is, e.g., an image memory device. The image memory device generally includes a random-access memory section (RAM section) for carrying out random access and a serial-access memory section (SAM section) for carrying out serial-access. The RAM section has a configuration similar to that of ordinary DRAM or SRAM, etc., and carries out access substantially in a similar manner. The SAM section includes one register in respective columns and serially accesses data of these registers. The RAM section and the SAM section can respectively provide accesses in an asynchronous manner. Further, data can be transferred between the RAM section and the SAM section.
The configuration and the operation for carrying out, in the SAM section, count up operation to generate counter address signals to decode them will now be described. The circuit configuration of a device related to this invention is shown in FIG. 7. This circuit includes counters 51a.about.51h, partial decoders 52a.about.52d, and serial decoders 53a.about.53n.
In this device, memory cells (not shown) are arranged in a form of matrix of 256 rows by 256 columns. In the case of carrying out serial access, it is necessary to select any one of 256 select lines SSL connected to respective registers. For this reason, an address signal of 8 bits is used.
A power supply voltage VDD is delivered to counters 51a.about.51h. Further, since the internal state of the circuit is unstable at the time of initially turning the power supply ON, signal SCTIN is inputted as an initial value. In these counters 51a.about.51h, counted up counter address signals A0S.about.A7S, /A0S.about./A7S are generated and outputted therefrom. These counter address signals A0S.about.A7S, /A0S.about./A7S are first partially decoded by partial decoders 52a.about.52d and are further decoded by serial decoders 53a.about.53n.
First, two sets of counter address signals are inputted to partial decoders 52a.about.52d, and are partially decoded. For example, counter address signals A0S and A1S, /A0S and /A1S outputted from counters 51a and 51b are inputted to partial decoder 52a. Thus, counter address decode signals ASA0.about.ASA3 are generated and outputted. Similarly, counter address signals A2S and A3S, /A2S and /A3S, A4S and A5S,/A4S and/A5S, A6S and A7S, and/A6S and /A7S are respectively inputted to other partial decoders 52b.about.52d. Thus, count address decode signals ASB0.about.ASB3, ASC0.about.ASC3, ASD0.about.ASD3 are outputted.
The counter address decode signals ASA0.about.ASA3, ASB0.about.ASB3, ASC0.about.ASC3 and ASD0.about.ASD3 thus outputted are inputted to 256 serial decoders 53a.about.53n in the state where they are combined four by four, at which they are decoded. For example, counter address decode signals ASA0, ASB0, ASC0, ASD0 are inputted to serial decoder 53a. Thus, a signal of high level or low level is outputted to one select line SSL0. By these serial decoders 53a.about.53n, any one of select lines SSL0.about.SSL255 is caused to be at high level.
The configurations of counters 51a and 51b are respectively shown in FIGS. 8(a) and (b), the configuration of partial decoder 52a is shown in FIG. 9, and the configuration of serial decoder 53a is shown in FIG. 3.
The counter 51a shown in FIG. 8(a) includes a NAND circuit 61a, inverters 63a, 66a, 67a, 70a and 72a.about.74a, NOR circuits 62a and 64a, and clocked inverters 65a, 68a, 69a and 71a, and the waveforms of input signal SCTIN, output signals A0S and T0, and respective nodes 503 and 504 are as shown in FIG. 10. As described above, power supply voltage VDD and signal SCTIN for giving initial value are inputted to counter 51a. Thus, counted up counter address signals A0S, /A0S are outputted. Counter address signal A0S of these signals is outputted from inverter 74a and is inputted to NOR circuit 62a. Moreover, signal T0 outputted from counter 51a is a CARRY signal for carrying address. This signal T0 is inputted to NAND circuit 61b (see FIG. 8(a)). A signal outputted from node 503 corresponds to an address count up signal indicating an address which has been counted up by CARRY signal TO and counter address signal A0S. From nodes 504 and 507, first and second latch signals for holding this address count up signal are respectively outputted.
First, when signal SCTIN falls down to low level as shown in FIG. 10, an address count up signal indicating an address counted up by CARRY signal TO and counter address signal A0S is outputted from node 503. This signal is converted into a first latch signal on node 504 through clocked inverter 65a, i.e., appears as first latch signal on node 504. When signal SCTIN rises up to high level for a second time, first latch signal is converted into a second latch signal on node 507 through inverter 67a, clocked inverter 69a, i.e., appears as a second latch signal on node 507. As a result, levels of counter address signals A0S, /A0S are switched.
Partial decoder 52a includes, as shown in FIG. 9, NAND circuit 81a.about.81d and inverters 82a.about.82d, and are adapted to be supplied with counter address signals A0S, A1S,/A0S, /A1S outputted from counters 51a and 51b. Thus, any one of counter address decode signals ASA0.about.ASA3 is selected and is caused to be at high level. The counter address decode signal of high level thus selected is outputted from partial decoder 52a. Similarly, counter address signals A2S, A3S,/A2S,/A3S, A4S, A5S,/A4S,/ASS, A6S, A7S,/A6S, /A7S respectively outputted from counters 51c and 51d, 51e and 51f, 51g and 51h are also inputted to other partial decoders 52b.about.52d. Further, any ones of counter address decode signals ASB0.about.ASB3, ASC0.about.ASC3, ASD0.about.ASD3 are caused to be at high level and are outputted from partial decoders 52b.about.52d, respectively.
Serial decoder 53a includes, as shown in FIG. 3, a NAND circuit 41 and an inverter 42, and is adapted to be supplied with counter address decode signals ASA0.about.ASD0 to output a signal of high level to select line SSL0 only when these signals are all at high level. Thus, a signal of high level is outputted from one decoder which has been supplied with signals that are all at high level of all serial decoders 53b.about.53n.
However, this device had the following problem. As described above, counters 51a.about.51h for carrying out count up and partial decoders 52a.about.52d for carrying out partial decode at the first stage were constructed as different circuits. Many wirings were required between the counters 51a.about.51h and partial decoders 52a.about.52d, resulting in increased chip area. Further, access speed was delayed by resistance and capacitance parasitic to the wiring.
In addition, this device also had the problem that current consumption is increased. Counter address signals A0S.about.A7S outputted from counters 51a.about.51h and counter address decode signals ASA0.about.ASA3, ASB3, ASC3, ASD3 outputted from partial decoders 52a.about.52d have waveforms as shown in FIG. 11.
As described above, signal SCTIN for providing an initial value as shown in FIG. 11 is inputted to decoders 51a.about.51h. First, the level of counter address signal A0S is switched by the first pulse, the levels of counter address signals A0S and A1S are switched by the second pulse, the level of counter address signal A0S is switched by the third pulse, and the levels of counter address signals A0S.about.A7S are switched by the fourth pulse.
Further, the levels of counter address signals ASA0 and ASA1 are switched by the first pulse of signal SCTIN, the levels of counter address signals ASA1 and ASA2 are switched by the second pulse, the levels of counter address signals ASA2 and ASA3 are switched by the third pulse, and the levels of counter address signals ASA3, ASA0, ASB3, ASB0, ASC3, ASC0, ASD3, ASD0 are switched by the fourth pulse.
The levels of respective signals are switched in this way, whereby charge/discharge operations take place on respective output terminals. As a result, currents are consumed. A change of current consumption versus passage of times is shown in FIG. 12. In this figure, time on the abscissa corresponds to timing at which the level of signal SCTIN in FIG. 11 is switched.
As apparent from FIG. 12, current consumption Icc increases every time signal SCTIN is switched. Further, this current consumption Icc increases to much degree according as the number of signals switched is increased.
When current consumption Icc increases, ground voltage Vss changes. By this noise based on such voltage change, any erroneous operation takes place. Particularly, in the memory device having RAM section and SAM section, there was the possibility that when they are operative in a manner asynchronous with each other, noise which has taken place in the SAM section is transmitted up to the RAM section through the same ground voltage terminal, so any erroneous operation may take place in the RAM section.